vMAGIC - Automatic Code Generation for VHDL

نویسندگان

  • Christopher Pohl
  • Carlos Paiz
  • Mario Porrmann
چکیده

Automatic code generation is a standard method in software engineering, improving the code reliability as well as reducing the overall development time. In hardware engineering, automatic code generation is utilized within a number of development tools, the integrated code generation functionality, however, is not exposed to developers wishing to implement their own generators. In this paper, VHDL Manipulation and Generation Interface (vMAGIC), a Java library to read, manipulate, and write VHDL code is presented. The basic functionality as well as the designflow is described, stressing the advantages when designing with vMAGIC. Two real-world examples demonstrate the power of code generation in hardware engineering.

برای دانلود رایگان متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید

ثبت نام

اگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید

منابع مشابه

Mppsocgen: A framework for automatic generation of mppsoc architecture

Automatic code generation is a standard method in software engineering since it improves the code consistency and reduces the overall development time. In this context, this paper presents a design flow for automatic VHDL code generation of mppSoC (massively parallel processing System-on-Chip) configuration. Indeed, depending on the application requirements, a framework of Netbeans Platform Sof...

متن کامل

Automatic Fixed-point Code Generation for Modelica using Dymola

This paper describes a Modelica package for fixedpoint arithmetics and automatic fixed point code generation for embedded systems and FPGA applications. Using Dymola [1] to investigate the dynamic behavior of the original model a fixed point representation is automatically generated. The model can then be simulated, using fixed point arithmetics to verify the fixed-point representation. Finally...

متن کامل

An FPGA Real-time Implementation of the Chen’s Chaotic System for Securing Chaotic Communications

In this paper, we present a new approach for real-time implementation of the Chen’s chaotic system on Field Programmable Gate Array (FPGA). The approach consists on using structural hardware description language (VHDL) with a fixed-point representation, contrary to some previous works which use somewhat non optimal VHDL code generation using automatic code generation tools. The obtained real-ti...

متن کامل

RASSP Benchmark-1 and -2: A Preliminary Assessment*

These two benchmarks required the development of a virtual prototype and a hardware prototype, respectively, of a Synthetic Aperture Radar processor. The two RASSP Developers chose different approaches: one used COTS components on custom boards with a methodology emphasis on detailed VHDL prototyping and board design and one used COTS computer boards with a methodology emphasis on efficient VHD...

متن کامل

ذخیره در منابع من


  با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید

عنوان ژورنال:
  • Int. J. Reconfig. Comp.

دوره 2009  شماره 

صفحات  -

تاریخ انتشار 2009